Manufacturing of semiconductor integrated circuits involves generation of desired circuits by repeating exposure, etching, deposition (plating), and planarization (polishing) on wafers to construct laminate structures. Recently, miniaturization of such circuits has progressed and thus high precision fabrication has been demanded.
For example, a copper wiring that is recently mainstream is formed by electro-chemical plating (ECP) of generating wiring grooves on an insulator and plating the wiring grooves with copper to fill the wiring grooves with copper. However, in the ECP, not only the wiring grooves but also the entire surface of the insulator are covered with the copper plating, and thus chemical mechanical polishing or chemical mechanical planarization (CMP) is used in polishing to expose a wiring pattern.
If what is obtained as a result of CMP includes a height difference of wafer surface, i.e., variation of height, a short circuit in the wiring or the like may be caused due to a property variation in the copper wiring or residual copper, and performance and yield are thereby decreased.
Ease of scraping differs among different materials in the CMP. For example, by the CMP, the copper wiring is scraped to a greater extent than an insulating layer. To suppress the height variation resulting in the CMP, importance of equalizing a wiring density, i.e., a proportion of wiring to a chip area has been conventionally noted. The wiring density is also called a metal density because the wiring is formed of a metal.
Inserting dummy wirings or dummy fills is known as a technique of equalizing the wiring density, as proposed for example in Japanese Laid-open Patent Publication No. 09-081622. In this insertion of dummy fills, a dummy wiring is inserted in an area having a low wiring density, electrically independent from a genuine wiring. Therefore, the dummy wiring does not function as an electric wiring, and enables adjustment of the wiring density to thereby adjust an amount to be scraped off by the CMP without affecting an operation of a circuit formed of the genuine wiring.
Conventional insertions of dummy fills includes a rule-based insertion of dummy fills and a model-based insertion of dummy fills, which are different from each other in their methods of determining necessity of inserting dummy wirings, positions to insert the dummy wirings, an amount of insertion, and a form of insertion.
The rule-based insertion of dummy fills involves a method of determining insertion of a dummy wiring according to a predetermined dummy fill rule during or after designing of a circuit layout. In the rule-based insertion of dummy fills, a separate analysis by a CMP simulator is necessary for predicting flatness. Therefore, it is difficult to carry out an optimization taking the flatness into consideration for each circuit layout, but a turn-around-time (TAT) is short.
The model-based insertion of dummy fills involves a method of performing a CMP simulation during designing of a circuit layout and inserting a dummy wiring to optimize flatness. The CMP simulation is a technique of estimating a height variation (flatness) resulting from the CMP based on a polishing condition and a layout pattern. In the model-based insertion of dummy fills, it is possible to carry out an optimization taking flatness into consideration for each circuit layout by performing the CMP simulation, and also to estimate the flatness. However, the CMP simulation takes time. In other words, there is a trade-off relationship between obtaining the flatness precisely by the simulation to optimize a dummy arrangement and shortening the time required for designing.
In the conventional techniques, the flatness evaluation and optimization of the dummy fill rule for each circuit layout, and the processing speed have been incompatible with each other. Accordingly, it has been an important challenge to estimate the flatness in a TAT equivalent to that by the rule-based dummy fill insertion and obtain a dummy fill rule that can realize a flatness equivalent to that by the model-based insertion of dummy fills.